Flexible low current oscillator for multiphase operations

ABSTRACT

A method for generating an oscillator signal uses a multiphase oscillator having a plurality of input stages and a reference stage. Each input stage produces an input stage voltage that represents a phase for the oscillator. The input stage voltages produced by each of the input stages are compared to a reference voltage produced by the reference stage. An input stage having a maximum input stage voltage is selected and an output of the selected input stage having the maximum input stage voltage is changed. A current need of the oscillator is detected with a negative feedback loop coupled to the reference stage. An appropriate supply current is provided to each input stage with the negative feedback loop.

CLAIM OF PRIORITY

This application is a continuation of and claims the priority benefit ofcommonly-assigned, co-pending U.S. patent application Ser. No.12/488,413 entitled “FLEXIBLE LOW CURRENT OSCILLATOR FOR MULTIPHASEOPERATIONS” to Behzad Mohtashemi, filed Jun. 19, 2009, the entiredisclosures of which are incorporated herein by reference.

FIELD OF THE INVENTION

This invention generally relates to an electrical circuit for generatinga cyclic signal and more particularly to a flexible oscillator with lowtransistor count, ability to oscillate to very high frequency, and lowcurrent consumption, which can be used in multiphase operations.

BACKGROUND OF THE INVENTION

Within nearly every electronic subsystem is some form of waveformgenerator that produces cyclical waveforms. The waveform generator isoftentimes referred to as an oscillator. Depending on the application,an oscillator can be used to source regularly spaced pulses or clocksignals. Oscillators are oftentimes rated depending on their stabilityand accuracy, frequency adjustability (i.e., tunability), gain of activecircuit, start-up time, power consumption, etc.

A type of oscillator commonly known as a relaxation oscillator is themost commonly used architecture for lower frequency oscillator designs.FIG. 1A is an electrical schematic diagram illustrating an example of aconventional relaxation oscillator. As shown in FIG. 1A, a relaxationoscillator 100 includes a capacitor C₁₀, a switching device SW₁₀ such asa field effect transistor, a comparator 102, a current source I₁₀ and aone-shot timer 104.

A voltage reference V_(Ref) is connected to the − input of thecomparator 102. A first terminal of the capacitor C₁₀ is connected tothe + input of the comparator 102. The second terminal of the capacitorC₁₀ is grounded. The output of the comparator 102 is electricallyconnected to the input of the one-shot timer 104, the output of which iselectrically coupled to a control terminal of the switch device SW₁₀.The switch device SW₁₀ is electrically connected between the firstterminal of the capacitor C₁₀ and ground and is used for discharging thefrequency-determining capacitor C₁₀. As shown in the voltage versus timegraph of FIG. 1B, the voltage on the capacitor is more or lesssaw-toothed in shape with a short flat spot 101 between successivesaw-teeth.

For these particular oscillators, the frequency is limited by the speedof the comparator 102. As current from the source I₁₀ charges thecapacitor C₁₀ the voltage at the (+) input of the comparator 102eventually reaches the reference voltage V_(Ref) and turns on comparator102. That triggers the one shot 104 to open the switch SW₁₀, whichdischarges the capacitor C₁₀ and sets the voltage back to zero. The oneshot 104 keeps the switch SW₁₀ on long enough to completely dischargethe capacitor C₁₀ so that the output is not erratic. In order to ensurethat the capacitor C₁₀ completely discharges, there will be a delay time101 between successive saw-teeth.

For low frequency, delay times in the comparator 102 are relativelysmall. But if switching is to be done at high frequency, the delay timebecomes large with respect to each saw-tooth cycle. Also, at highfrequency, e.g. 5 MHz, a high switching current, e.g., 1 mA is needed.The current source that charges up the capacitor C₁₀ coupled to the oneshot 104 increases as the input voltage increases. So, for example, at5.0V the current source I₁₀ may be able to deliver 5 μA, and at 2.5 itcan deliver only 1 μA. Thus, at 5.0V, for example, the capacitor chargesup 5 times faster than at 2.5V. So, at 5.0V, the flat response is muchless than what it is at 2.5V. In a low frequency where switchingfrequency is at 500 KHz, it might not be a problem for the one shot 104to vary from 50 ns to 70 ns, but in a high frequency oscillation, e.g.,greater than 3 MHz, it matters very much to have variations from 50 ns,to 100 ns.

Since one shot properties vary with supply voltage, the flat spotbetween sawtooth waves changes with supply voltage and also varies withtemperature, which is not desirable. As a result, relaxation oscillatorsare only good for frequencies of about 1 MHz and below. In addition,these oscillators are not well suited for multiphase systems. In aconventional multiphase system, each phase need its own particularoscillator and comparator. Furthermore, the conventional comparator isnot cheap and the oscillator consumes a lot of current. High currentconsumption is undesirable in many applications, such as portabledevices.

It is within this context that embodiments of the present inventionarise.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a circuit diagram of a conventional relaxation oscillator.

FIG. 1B shows a signal profile of the circuit of FIG. 1A.

FIGS. 2A-2B are circuit diagrams illustrating the principles ofoperation of the oscillators and the reference stage according toembodiments of the present invention.

FIG. 3A is a circuit diagram of an NMOS two phase oscillator accordingto an embodiment of present invention.

FIG. 3B is a circuit diagram of a PMOS two phase oscillator according toan embodiment of present invention.

FIGS. 3C-3D show signal profiles at nodes N₁ and N₂ in the electricalcircuits of the type shown in FIGS. 3A-3B respectively.

FIG. 3E shows the combined signal profiles of nodes N₁ and N₂.

FIG. 3F shows a circuit diagram of a NMOS two phase oscillator with analternative reference stage.

FIG. 4A is a circuit diagram of a three phase oscillator according to anembodiment of the present invention.

FIGS. 4B-4D shows signal profile at nodes N₁, N₂ and N₃ of FIG. 4A at anoscillation frequency of 50 MHz.

FIG. 4E shows signal profile at nodes N₁, N₂ and N₃ of FIG. 4A at anoscillation frequency higher than 50 MHz.

FIG. 5A is a circuit diagram of a four phase oscillator according to anembodiment of the present invention.

FIGS. 5B-5E shows signal profile at nodes N₁, N₂, N₃ and N₄ of FIG. 5Aat an oscillation frequency higher than 50 MHz.

FIG. 5F shows signal profile at nodes N₁, N₂, N₃ and N₄ of FIG. 5A at anoscillation frequency higher than 50 MHz.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

Embodiments of the present invention are directed to oscillators thatovercome the disadvantages associated with prior art relaxationoscillators. Oscillator designs in accordance with embodiments of thepresent invention eliminate the need for a conventional comparator. Theoscillator is generally comprised of one or more differential inputstages that may have as many input stages as the number of phases neededwith a small number of active components. Each differential stage actsas a maximum selector stage. As used herein, the term “maximum selector”refers is a circuit having multiple input stages (sometimes referred toherein as “phase stages”) that chooses the maximum voltage of thevoltages of the different input stages. Selection of a given input stageby the maximum selector causes an output of the selected input stage tochange. The current supplied to a given input stage may be varied as theoscillator's needs change. For example, a negative feedback loop coupledto the reference stage may be configured to detect a current need of theoscillator and provide an appropriate supply current to each input stageto meet the detected current need.

According to an embodiment of the invention, an oscillator apparatus maycomprise a reference stage and two or more phase stages including afirst stage and a last stage. The reference stage has a referencecurrent source and a first reference transistor having a gate coupled toa voltage reference and a drain coupled to the reference current source.By way of example, and not by way of limitation, each of the phasestages may include a transistor, first and second current sources, acapacitor, a switch, and a logic block. The transistor has a draincoupled to the first current source, a gate coupled to a node and asource coupled to a source of the reference transistor in the referencestage. The capacitor has a first terminal coupled to the node and asecond terminal connected to ground. The switch is coupled between thefirst and second terminals of the capacitor. The second current sourceis coupled to the node.

Basically, the logic block for a given phase stage is used to latch onthe switch for that phase stage, and reset the switch for the next phasestage. In other words, when a phase stage is selected by the maximumselector, the logic block deactivates the selected phase stage, andactivates the next phase stage (which corresponds to the next phase ofthe oscillator). The logic block for each phase stage may be formed inmany different ways. An example of a logic block is shown which includesan inverter and a set-reset latch. An input of the inverter for a givenphase stage is coupled to the drain of the transistor for that phasestage. The output of the inverter for a given phase stage is coupled toa set input for the latch for that phase stage. An output of the latchfor a given phase stage is coupled to the switch for that phase stage.The output of the inverter for a given phase stage is also coupled tothe reset input of the set-reset latch in a subsequent phase stage. Theoutput of the inverter for the last stage is coupled to the reset inputof the set-reset latch in the first stage.

FIG. 2A is a circuit diagram illustrating an input stage (or phasestage) of a phase oscillator 200. As shown in FIG. 2A, the oscillator200 includes a reference stage 202 and a phase stage 204. The referencestage 202 includes a reference field effect transistor T_(ref) having adrain D_(ref) electrically coupled to a first reference current sourceI_(ref), gate G_(ref) electrically connected to a voltage referenceV_(ref) and a source S_(ref) coupled to an input of a second referencecurrent source I_(ref)′, which may supply a reference current of up to,e.g., about twice the current supplied by the first reference currentsource I_(ref). By way of example, the reference transistor T_(ref) maybe a metal oxide semiconductor (MOS) device. By way of example, thefirst reference current source I_(ref) may supply a current of about 1μA and the second reference current source I_(ref)′ may supply a currentof about 2 μA and the reference voltage V_(ref) may be about 1.2 volts.

The phase stage 204 also includes a transistor T₁ having a source S₁, agate G₁, and a drain D₁. The source S₁ is connected to the sourceS_(ref) of the reference transistor T_(ref), at a first junction J₁. Thegate G₁ is coupled to a second junction J₂ and the drain D₁ is connectedto the output of a current source I₁ that supplies a current roughly thesame as the current supplied by the first reference current sourceI_(ref). The oscillator 200 also includes a capacitor C having a firstterminal connected to the junction J₂ and a second terminal that isgrounded. The oscillator 200 also includes a switch SW that permitscurrent to flow between the second junction J₂ and ground to dischargecapacitor C when a control electrode of the switch SW receives an inputtrigger signal. Input sides of current sources I_(ref), I₁ and a thirdcurrent source I₁′ are coupled to a third junction J₃. The output of thethird current source I₁′ is coupled to the junction J₂.

Operation of the oscillator 200 may proceed as follows. Supposeinitially, the trigger signal turns switch SW on, therefore thetransistor T₁ is off since the gate G₁ is coupled to ground. Thetransistor T_(ref) is on due to the reference voltage V_(ref) applied tothe gate G_(ref) of the reference transistor T_(ref). The larger currentfrom the second reference source I_(ref)′ pulls the drain D_(ref) of thereference transistor T_(ref) down, but the smaller current from thesource I₁ pulls up the drain D₁ of transistor T₁.

After the switch SW is turned off, the current from the third currentsource I₁′ charges up the capacitor C and slowly turns the transistor T₁on and the reference transistor T_(ref) off as the gate G₁ of thetransistor T₁ goes above the reference voltage V_(ref). The currentsource L_(ref)′ pulls down the voltage at the drain D₁ of the transistorT₁ and pulls up the voltage at the first junction J₁ and at the drainD_(ref) of the reference transistor T_(ref). This situation remainsuntil the switch SW turns on again. Digital output signals may beobtained from the voltages at the drains D₁ and D_(ref) of thetransistors T₁ and T_(ref). In order for the oscillator to operate at arelatively high rate, the current from the second reference currentsource I_(ref)′ should be relatively large, as discussed above.

Alternatively, instead of using a constant current I_(ref)′, a currentcontrol may use negative feedback based on the voltage between the firstreference source I_(ref) and the reference transistor T_(ref) (which maybe referred to as the first reference transistor) may be used to controlthe current from the transistor T₁ through the junction J₁. For example,FIG. 2B is an electrical diagram of an alternative oscillator 210, thatis a variation on the oscillator 200 shown in FIG. 2A. In addition tothe components described above with respect to FIG. 2A, a referencestage 212 of the oscillator 210 includes a current control in the formof second reference transistor T_(ref)′ (e.g., a MOS transistor) havinga drain D_(ref)′ coupled to first junction J₁, a gate G_(ref)′ coupledto the drain D_(ref) of first reference transistor T_(ref) and a sourceS_(ref)′ connected to ground. It is noted that in this exampleillustrated in FIG. 2B, the reference transistor T_(ref)′ is an N-type(or n-channel) device. Alternatively, the reference transistor T_(ref)′may be a P-type (or p-channel) device, in which case the source S_(ref)′may be coupled to a common voltage V_(cc). The first reference currentsource I_(ref) acts as a fixed reference current source. If the voltageat junction J₁ goes high (e.g., when T₁ turns on) the drain D_(ref) offirst reference transistor T_(ref) and gate G_(ref)′ of the secondreference transistor T_(ref)′ to be pulled high, which turns the secondreference transistor T_(ref)′ more on which increases the supply currentI_(s) and pulls junction J₁ back down. Without the negative feedback, anincrease of voltage at junction J₁ would cause the first referencetransistor T_(ref) to turn off because its gate-to-source voltage (i.e.,V_(ref) minus the voltage at junction J₁) decreases. Conversely, if thevoltage at junction J₁ goes low it pulls the gate G_(ref)′ of thetransistor T_(ref)′ low, which pulls the junction J₁ back up. If thesecond reference transistor T_(ref)′ cannot supply sufficient current,it pulls up the voltage at the drain D_(ref) of the transistor T_(ref)and at the junction J₁ which causes the second reference transistorT_(ref)′ to open more until it provides the appropriate supply currentI_(s). This way, the first reference transistor T_(ref) is always on andallows the current supplied by supply I_(ref) to go through, no matterwhat the input is from transistor T₁. The second reference transistorT_(ref)′ changes the amount of current it allows through such that thevalue of current source I_(ref) always flows through referencetransistor T_(ref). As a result of I_(ref), T_(ref), and T_(ref′), thereis a negative feedback in the circuit of FIG. 2B. Because of thisnegative feedback, the supply current I_(s) of the circuit 210 changesto meet the current demand of the system.

The secondary reference transistor T_(ref)′ acts as a variable resistorthat throttles the current of the reference current source I_(ref) in anegative feedback manner in response to changes in the current throughjunction J₁. Alternatively, another device capable of delivering anegative feedback loop such as an operational amplifier or variableresistor may be used as the current control to adjust the supply currentI_(s) in response to changes in the voltage at junction J₁ to providethe desired negative feedback control of the current through thejunction J₁.

Two or more phase stages of the type shown in FIG. 2A, 2B may becombined together with a reference block of the type shown in FIG. 2B toprovide a multiple phase oscillator according to an embodiment of thepresent invention. By way of example, and not by way of limitation, FIG.3A is an electrical diagram illustrating a two phase oscillator 300according to an embodiment of the present invention. As shown in FIG.3A, the oscillator 300 includes two phase stages 302, 304 and onereference stage 306. The reference stage 306 is similar to the referencestage 212 of the oscillator 210 described above in FIG. 2B.

By way of example, the first phase stage 302 may include a n-type MOStransistor T₁ having a drain D₁ coupled to a current source I₁, whichmay supply a current of about 1 uA through a junction J₁, a gate G₁coupled to a first node N₁, and a source S₁ coupled to a junction J₇ ofthe reference stage 306. The first phase stage 302 also includes acapacitor C₁ having a first terminal coupled to secondary current sourceI₁′ through the first node N₁ and a second terminal is connected to theground. A switch SW₁, which can be an n-type MOS transistor, isconnected in parallel to the capacitor C₁ with a source grounded andhaving a gate coupled to an output of a latch L₁. The first phase stage302 may further include a logic block 303 which includes an inverterINV₁ having an input coupled to the transistor T₁ at the junction J₁ andan output coupled to an input of the latch L₁. A one-shot timer OS₁ maybe optionally coupled between the inverter INV₁ and the latch L₁. Insuch a case, the output of the inverter INV₁ may be regarded as beingindirectly coupled to the latch L₁. The logic block shown here is onlyan example and may be replaced with a similarly functioning circuitblock.

The second phase stage 304 includes similar components as the firstphase stage 302. The second phase stage 304 may include a n-channel MOStransistor T₂ having a drain D₂ coupled to a current source I₂ of about1 uA through a junction J₂, a gate G₂ coupled to secondary currentsource I₂′ through a second node N₂, and a source S₂ coupled to thejunction J₇. The second phase stage 304 also includes a capacitor C₂that is of equal capacitance to the capacitor C₁. The capacitor C₂ has afirst terminal coupled to the second node N₂ and a second terminal isconnected to the ground. A switch SW₂, which can be a n-channel MOStransistor, is coupled to the capacitor C₂, and includes a sourceconnected to the ground and a gate coupled to an output of a latch L₂.The second phase stage 304 may further include a logic block 305 whichincludes an inverter INV₂ having an input coupled to the transistor T₂at the junction J₂ and an output coupled to an input of the latch L₂. Aone-shot timer OS₂ is optionally coupled between the inverter INV₂ andthe latch L₂. The one-shot timers OS₁, OS₂ provide digital outputsignals if needed.

The reference stage 306 may operate in a manner similar to that ofreference stage 212 as described above with respect to FIG. 2B. Thereference stage 306 may operate with or without feedback control of thecurrent. In the example shown in FIG. 3A, the second referencetransistor T_(ref)′ provides negative feedback control of the currentthrough the junction J₇ from the transistors T₁, T₂, and T_(ref).

As shown in FIG. 3A, the output of the one-shot timer OS₁ is connectedto the set input S of the latch L₁ and to the Reset input R of the latchL₂. Similarly, the output of one-shot timer OS₂ is connected to a Setinput S of the latch L₂ and a Reset input R of the latch L₁. It is notedthat if the one-shot timers are not used, the outputs of the invertersINV₁, INV₂ would be coupled directly to the latches.

The circuit 300 operates as a maximum selector that chooses as itsoutput the maximum of the voltages of the phase stages 302, 304. In theexample depicted in FIG. 3A, there are three voltages in the system,V_(ref), and the voltages at nodes N₁, N₂ (referred to as V_(n1), andV_(n2), respectively). The architecture shown in FIG. 3A always picksthe largest of the voltages V_(n1), and V_(n2) and V_(ref). For example,if initially V_(ref) is 1.2V, and both N₁ and N₂ are at 0 volts. As soonas either V_(n1) or V_(n2) has risen above V_(ref), it is recognized bythe architecture shown and it will be selected. For example, if V_(n2)has risen above V_(ref), then phase stage 304 is selected, and thetransistor T₂ turns on. Because of the negative feedback in thereference stage 306, the reference transistor T_(ref) still stays on aswill be explained below. With the transistor T₂ on, the voltage at J₁ ispulled low, which triggers the logic unit 305.

The supply current I_(s) is not fixed and it varies with the need of thesystem. In FIG. 3A, the arrangement of T_(ref) and T_(ref)′ provides anegative feedback, which means it will supply the required current forthe intended architecture. The negative feedback ensures that T_(ref)always allows the value of the reference current source I_(ref) through,but also adjusts to provide the demand for current from the rest of thesystem. For example, when phase stage 304 is selected, the secondreference transistor T_(ref)′ allows the supply current I_(s) through inthe amount of I_(ref) plus I₂. However, when either of the transistorsshown, T₁ or T₂, turns on, there are parasitic capacitances that must becharged before these transistors can turn on. So the more currentavailable, the faster these capacitances can be charged up and thequicker the transistors can turn on. During that transient, the supplycurrent I_(s) will be increased due to the negative feedback onT_(ref)′. The negative feedback detects the current demand of thesystem, and provides the supply current I_(s) accordingly. Thus thenegative feedback enables a more efficient, robust, and fasteroscillator circuit. No matter how many stages are used, and what thetransient current demand is, the negative feedback ensures that theappropriate supply current I_(s) is provided.

FIG. 3B is an electrical diagram showing an alternative two phaseoscillator 310, which includes similar components as the oscillator 300,except the transistors T₁, T₂, T_(ref) and T_(ref)′ and the switches SW₁and SW₂ are p-channel MOS transistors. In this embodiment, the secondterminals of the capacitors C₁, C₂, the sources of the switches SW₁, SW₂and the source of the secondary reference transistor T_(ref)′ arecoupled to a voltage Vcc instead of grounded. In other words, thepositions of the Vcc and the ground are switched and so are thedirections of the current sources I₁, I₁′, I₂, I₂′ and I_(ref) incircuit 310, as compared to circuit 300 of FIG. 3A. In the logic portionof each phase stage for two phase oscillator 310, the inverter is placedbetween the latch and the switch, rather than between the one shot andthe junction (e.g., J₁).

Speed of oscillation of the oscillators 300 and 310 is regulated by theamount of current provided by current sources I₁′, I₂′, and size of thecapacitors C₁, C₂. The oscillators 300 and 310 can be used in dual phaseconverters.

The oscillators 300, 310 may operate as follows. At an initial state theswitch SW₁ is off and the switch SW₂ is latched on by latch L₂. As aresult, the transistor T₂ is off. Initially, the voltage at node N₁ islow, so transistor T₁ is also off. Current from source I₁′ charges thecapacitor C₁ from 0 to a reference voltage V_(ref) (e.g., 1.2 V). Thecapacitor C₁ charges up and when it reaches V_(ref) that stage isselected by the maximum selector and the transistor T₁ turns on. Currentfrom the source I₁ pulls up the voltage at J₇, which causes the negativefeedback loop to turn on secondary reference transistor T_(ref)′ more inorder to compensate the additional current. With the current flowingthrough T_(ref)′ higher than the current supplied by supply I₁, thevoltage at the drain D₁ of the transistor T₁ is pulled down, which pullsthe input of the inverter INV₁ low. As a result, the output of theinverter INV₁ is high, which sets the latch L₁ and resets the latch L₂.This turns on the switch SW₁ and turns off the switch SW₂.

Similarly, when the switch SW₂ is off (and switch SW₁ is latched on),the current source I₂′ is charging the capacitor C₂ from 0 to V_(ref)(e.g., 1.2 V). When the voltage on the capacitor C₂ reaches V_(ref), thetransistor T₂ turns on. The reference transistor T_(ref)′ supplies morecurrent than the source I₁ so that pulls drain D₂ of the transistor T₂down. The input of the INV₂ goes low and the output of INV₂ goes high,which sets the latch L₂, turning on the switch SW₂ and resetting thelatch L₁. The output of the latch L₁ therefore goes low and the switchSW₁ turns off.

As may be seen from the foregoing, when the voltage at node N₂ turns ontransistor T₂, the voltage at N₁ is turns off transistor T₁ and viceversa. Consequently, the oscillator 300 or 310 can produce oscillationsignals in two different phases. FIGS. 3C-3D show simulated outputsignal profiles at nodes N₁ and N₂ in the electrical circuits shown inFIGS. 3A-3B operating at 33.3 MHz. As shown in the figures, the sawtoothwaveforms are 180 degrees apart. FIG. 3E shows the two sawtoothwaveforms of FIGS. 3C-3D combined together. Note that because there aretwo input stages, the capacitor for one stage can begin charging as soonas the capacitor for the other stage starts to discharge. Thus there isno need to wait for the capacitor to fully discharge before starting thenext cycle, and the delay time 101 of FIG. 1B is eliminated. The oneshot timers in this invention are optional and are only used to helpprovide digital signals. They do not interfere with the timing of thecircuit.

Alternatively, the second reference transistor T_(ref) may be replacedby a current source such as I_(ref)′ of FIG. 2A, however this embodimentwould not have negative feedback. In another alternative embodiment, asshown in the circuit 300′ of FIG. 3F, the negative feedback for thereference stage 306′ may further include an op amp OA_(ref) and aresistor R_(ref). The resistor R_(ref) is connected in series betweenthe source of second reference transistor T_(ref)′ and ground. Theoutput of the op amp OA_(ref) is connected to the gate of secondreference transistor T_(ref)′, one input of op amp OA_(ref) is connectedbetween second reference transistor T_(ref)′ and resistor R_(ref), andthe other input of op amp OA_(ref) is connected to drain of firstreference transistor T_(ref) having potential V. The supply currentI_(s) flowing through second reference transistor T_(ref)′ is equal toI_(s)=V_(x)/R_(ref). As with the circuit 300 of FIG. 3A, the negativefeedback detects the oscillator current need, and provides theappropriate supply current L. Otherwise the circuit 300′ is the same asthe circuit 300 of FIG. 3A.

The oscillator depicted in FIGS. 3A, 3B may be extended to any number ofphases simply by adding more phase stages. By way of example, and not byway of limitation, a three phase oscillator can be made by addinganother phase module to the circuit of the two phase oscillator of thetype depicted in FIGS. 3A-3B. FIG. 4A is an electrical diagramillustrating a three phase oscillator 400. Such an oscillator may beused, e.g., in a three phase voltage converter. The oscillator 400includes three phase stages 402, 404, 406 and one reference stage 408.The reference stage 408 is similar to the reference stage 212 of theoscillator 210 described above in FIG. 2B, which includes two referencetransistors T_(ref) and T_(ref)′. The second reference transistorT_(ref)′ is configured as described above to provide negative feedbackcontrol of the current through first reference transistor T_(ref)regardless of the current from the transistors of the phase stages.

The first and second phase stages 402 and 404 are similar to the firstand second phase stages 302 and 304 of the two phase oscillator 300 asdescribed in FIG. 3A. The first phase stage 402 may include a n-channelMOS transistor T₁ having a drain D₁, a gate G₁ and a source S₁. Thedrain D₁ is coupled to a current source I₁ of, e.g., about 1 uA througha junction J₁. The gate G₁ is coupled to a first node N₁. The source S₁is coupled to junction J₅ in the second phase stage 404, a junction J₆in the third phase stage 406 and connected to a junction J₇ in thereference stage 408. The first phase stage 402 also includes a capacitorC₁ having a first terminal coupled to secondary current source I₁′through the first node N₁ and a second terminal is connected to theground. A switch SW₁, which can be a MOS transistor, is coupled to thecapacitor C₁ with a source grounded and having a gate coupled to anoutput of a first latch L₁. The first phase stage 402 may furtherinclude a first inverter INV₁ having an input coupled to the currentsource I₁ at the junction J₁ and an output coupled to an input of thefirst latch L₁. A one-shot timer OS₁ may optionally be coupled betweenthe first inverter INV₁ and the first latch I₄.

The second phase stage 404 includes a MOS transistor T₂ having a drainD₂ coupled to a current source I₂ of, e.g., about 1 uA through ajunction J₂, a gate G₂ coupled to secondary current source I₂′ through asecond node N₂, and a source S₂ coupled to the junction J₅. The secondphase stage 404 also includes a capacitor C₂ having a first terminalcoupled to the second node N₂ and a second terminal is connected to theground. A switch SW₂, which can be a MOS transistor, is coupled to thecapacitor C₂, and includes a source connected to the ground and a gatecoupled to an output of a second latch L₂. The second phase stage 404may further include a second inverter INV₂ having an input coupled tothe current source I₂ at the junction J₂ and an output coupled to aninput of the second latch L₂. A one-shot timer OS₂ may optionally becoupled between the second inverter INV₂ and the second latch L₂.

The third phase stage 406 includes a MOS transistor T₃ having a drainD₃, gate G₃, and a source S₃. The drain D₃ is coupled to a currentsource I₃ of, e.g., about 1 uA through a junction J₃. The gate G₃ iscoupled to secondary current source I₃′ through a third node N₃. Thesource S₃ is coupled to the junction J₆. The third phase stage 406 alsoincludes a capacitor C₃ of equal capacitance to the capacitors C₁, C₂.The period for each phase is determined by the values of the secondarycurrent sources I₁′, I₂′, I₃′, and of the capacitors C₁, C₂, C₃ sincethey determine how fast the voltage across the capacitors increase. Fora symmetrical oscillator with equal phases, the values of the currentsources and of the capacitors should be equal. However, if unequalphases are desired, those values may be altered accordingly. Thecapacitor C₃ has a first terminal coupled to the third node N₃ and asecond terminal is connected to the ground. A switch SW₃, which can be aMOS transistor, is coupled to the capacitor C₃, and includes a sourceconnected to the ground and a gate coupled to an output of a third latchL₃. The third phase stage 406 may further include a third inverter INV₃having an input coupled to the current source I₃ at the junction J₃ andan output coupled to an input of the third latch L₃. A one-shot timerOS₃ may optionally be coupled between the third inverter INV₃ and thethird latch L₃.

In general, it is not necessary for the reference current I_(ref) to beequal to I₁, I₂, and I₃. It is also not also necessary for I₁′=I₂′=I₃′.However, if a symmetrical oscillator is desired, then the secondarycurrent sources should be equal, I₁′=I₂′=I₃′, as should be thecapacitances of capacitors C₁=C₂=C₃.

As shown in FIG. 4A, the output of the one-shot timer OS₁ is connectedto a set S of the latch L₁ and a reset R of the latch L₂. The output ofthe one-shot timer OS₂ is connected to a set S of the latch L₂ and areset R of the latch L₃. The output of the one-shot OS₃ is connected toa set S of the latch L₃ and a reset R of the latch L₁. The one-shottimers OS₁, OS₂, OS₃ can provide digital output signals if needed. Ifthe one-shot timers OS₁, OS₂, OS₃ are not used, the outputs of theinverters INV₁, INV₂, INV₃ may be directly coupled to the latches.

The reference stage 408 may operate in a manner similar to thatdescribed above with respect to FIG. 2B. The reference stage 408 mayoperate with or without feedback control of the current. In the exampleshown in FIG. 4A, the second reference transistor T_(ref)′ providenegative feedback control of the current through the junction J₇ fromthe transistors T₁, T₂, T₃, and T_(ref).

The speed of oscillation of the oscillator 400 is regulated by thecurrent supplied by sources I₁′, I₂′, I₃′ and size of capacitors C₁, C₂,C₃. The oscillator 400 may operate as follows. At an initial stage, theswitch SW₁ is off and the switches SW₂ and SW₃ are on. The voltage atthe first node N₁ is ramped up by the current from the current sourceI₁′ until it reaches the reference voltage V_(ref), which turns ontransistor T₁ and pulls the drain D₁ of transistor T₁ down. This setsthe latch L₁ and resets the latch L₂. Therefore the switch SW₁ turns onand the switch SW₂ turns off; the switch SW₃ remains latched on.

Similarly, with switch SW₂ off, when the voltage at the node N₂ goesabove V_(ref) due to the current from the source I₂′, the drain D₂ ofMOS transistor T₂ is pulled down. This sets the second latch L₂ andresets the third latch L₃. As a result, the second switch SW₂ turns onand the third switch SW₃ turns off. When the voltage at the node N₃ goesabove V_(ref) as a result of the current from the current source I₃′,the voltage on the drain D₃ of the transistor T₃ is pulled down. Thissets the latch L₃ and resets the latch L₁. As a result, the switch SW₃turns on and the switch SW₁ turn off, which is back to the initialstage. The three phases of the oscillator 400 correspond to the voltagesat the nodes N₁, N₂ and N₃. To the oscillation frequency the capacitorsC₁, C₂ or C₃ may be decreased and the current source I₁′, I₂′ and I₃′should be increased.

FIGS. 4B-4D show simulated signal profiles at nodes N₁, N₂ and N₃ in theelectrical circuits shown in FIG. 4A. As shown in the figures, thesawtooth waveforms are 120 degrees apart. FIG. 4E shows the sawtoothwaveforms of FIGS. 4B-4D superimposed on each other.

A four phase oscillator may be made by adding another phase module tothe circuit of the three phase oscillator of the type depicted in FIG.4A. FIG. 5A is an electrical diagram illustrating a three phaseoscillator 500, which includes four phase stages 502, 504, 506, 508 andone reference stage 510. The reference stage 510 is similar to thereference stage 212 of the oscillator 210 described above in FIG. 2B,which includes two reference transistors T_(ref) and T_(ref)′, which maybe MOS transistors. The first three phase stages 502, 504, 506 areconfigured substantially the same as stages 402, 404, and 406 as shownin FIG. 4A with a few minor differences. Specifically, junction J₆ ofthe third reference stage 506 is coupled to a similar junction J₈ in thefourth reference stage 508, which is coupled to the junction J₇ in thereference stage. Also the output of one-shot timer OS₃ is connected tothe reset R of latch L₄ and the reset R of latch L₁ is connected to theoutput of one-shot timer OS₄.

The fourth phase stage 508 may include transistor T₄, e.g., a MOStransistor, having a drain D₄, a gate G₄ and a source S₄. The drain D₄is coupled to a current source I₄ of, e.g., about 1 uA through ajunction J₄ The gate G₄ is coupled to secondary current source I₄′through a fourth node N₄, and the source S₄ coupled to the junction J₈.The fourth phase stage 508 also includes a capacitor C₄, which isgenerally of equal capacitance to the capacitors C₁, C₂, C₃. Thecapacitor C₄ has a first terminal coupled to the fourth node N₄ and asecond terminal is connected to the ground. A switch SW₄, which can be aMOS transistor, is coupled to the capacitor C₄, and includes a sourceconnected to the ground and a gate coupled to an output of a fourthlatch L₄. The fourth phase stage 508 may further include a fourthinverter INV₄ having an input coupled to the current source I₄ at thejunction J₄ and an output coupled to an input of the latch L₄. Aone-shot timer OS₄ may optionally be coupled between the fourth inverterINV₄ and the fourth latch L₄.

As shown in FIG. 5A, the output of the one-shot timer OS₂ is connectedto a set S of the latch L₁ and a reset R of the latch L₂. The output ofthe one-shot timer OS₂ is connected to a set S of the latch L₂ and areset R of the latch L₃. The output of the one-shot OS₃ is connected toa set S of the latch L₃ and a reset R of the latch L₄. The output of theone-shot OS₄ is connected to a set S of the latch L₄ and a reset R ofthe latch L₁. The speed of oscillation of the oscillator 500 isregulated by size of the current from sources I₁′, I₂′, I₃′, I₄′ andsize of the capacitors C₁, C₂, C₃, and C₄.

The reference stage 510 may operate in a manner similar to thatdescribed above with respect to FIG. 2B. The reference stage 510 mayoperate with or without feedback control of the current. In the exampleshown in FIG. 5A, the second reference transistor T_(ref)′ providesnegative feedback control of the current through the junction J₇ fromthe transistors T₁, T₂, T₃, T₄, and T_(ref).

The operation of the oscillator 500 is similar to the operation of theoscillator 400 as described above. At the initial stage, the firstswitch SW₁ is off and the switches SW₂, SW₃ and SW₄ are on. The voltageat the first node N₁ ramps up due to the current from the source I₁′until it reaches V_(ref), which pulls the drain D₁ of transistor T₁down. This sets the first latch L₁ and resets the second latch L₂.Therefore, the first switch SW₁ turns on and the second switch SW₂ turnsoff.

Similarly, when the voltage at the second node N₂ goes above thereference voltage V_(ref) due to the current from the source I₂′, thedrain D₂ of the transistor T₂ is pulled down. This sets the second latchL₂ and resets the third latch L₃. As a result, the second switch SW₂turns on and the third switch SW₃ turns off.

When the voltage at the third node N₃ goes above the reference voltageV_(ref) due to the current from the source I₃′, the drain D₃ of thetransistor T₃ is pulled down. This sets the third latch L₃ and resetsthe fourth latch L₄. As a result, the third switch SW₃ turns on and thefourth switch SW₄ turn off.

When the voltage at the fourth node N₄ goes above the reference V_(ref)as a result of the current from the source I₄′, the drain D₄ of thetransistor T₄ is pulled down. This sets the fourth latch L₄ and resetsthe first latch L₁. As a result, the fourth switch SW₄ turns on and thefirst switch SW₁ turn off, which is back to the initial stage.

The four phases can be observed at nodes N₁, N₂, N₃ and N₄. To increasefrequency of the oscillator, the capacitors C₁, C₂, C₃ or C₄ should bedecreased and the current sources I₁′, I₂′, I₃′ and I₄′ should beincreased. The one-shot timers OS₁, OS₂, OS₃, OS₄ can provide digitaloutput signals if needed. If the one-shot timers OS₁, OS₂, OS₃, OS₄ arenot used, the outputs of the inverters INV₁, INV₂, INV₃, INV₄ may bedirectly coupled to the latches.

FIGS. 5B-5E show simulated signal profiles at nodes N₁, N₂, N₃ and N₄ inthe electrical circuits shown in FIG. 5A at an oscillation frequency of50 MHz. As shown in the figures, the sawtooth waveforms are 90 degreesapart. FIG. 5F shows the sawtooth waveforms of FIGS. 5B-5D superimposedupon each other.

Oscillators according to embodiments of the present invention asdescribed above may be used for any switching systems. It is estimatedthat such oscillators can oscillate from very low frequency up to about50 MHz based on low voltage CMOS process. A faster process will allowfaster oscillation frequencies. Another advantage of such oscillators isthat they can change their bias current as demand changes duringtransients. The number of phases can easily be changed as the complexityof the system changes. In addition, the one shot timers and invertersused in the phase modules take up relatively little real estate on achip. Spread of frequency over the voltage range is only a few percentfrom 2.5 to 5 volts. Furthermore, the oscillators of the type describedabove consume low current because a conventional comparator is notrequired and the reference stage can vary the current as required.

While the above is a complete description of the preferred embodiment ofthe present invention, it is possible to use various alternatives,modifications and equivalents. Therefore, the scope of the presentinvention should be determined not with reference to the abovedescription but should, instead, be determined with reference to theappended claims, along with their full scope of equivalents. Anyfeature, whether preferred or not, may be combined with any otherfeature, whether preferred or not. In the claims that follow, theindefinite article “A”, or “An” refers to a quantity of one or more ofthe item following the article, except where expressly stated otherwise.The appended claims are not to be interpreted as includingmeans-plus-function limitations, unless such a limitation is explicitlyrecited in a given claim using the phrase “means for.”

What is claimed is:
 1. A method for generating an oscillator signal witha multiphase oscillator, the method comprising: producing two or morevoltages by two or more input stages, wherein each input stage includinga transistor represents a phase for the oscillator and wherein the twoor more voltages are gate voltages of the corresponding transistors;outputting one of the two or more voltages that exceeds a referencevoltage level as an output voltage of the oscillator by turning on thetransistor of the input stage that has its gate voltage exceeding thereference voltage level and turning off other transistors, wherein thereference voltage level is corresponding to a reference voltage producedby a reference stage; and providing an appropriate supply current toeach input stage with a negative feedback loop.
 2. The method of claim1, the reference stage further comprises: a fixed current source inseries with a reference transistor, wherein the negative feedback loopis configured to cause the reference transistor to allow a fixed currentvalue of the fixed current source to pass through the referencetransistor.
 3. The method of claim 1, wherein providing an appropriatesupply current to each input stage further includes applying a currentcontrol to a source of a reference transistor, wherein the currentcontrol is configured to regulate a total current from the transistorsin the input stages and the reference transistor in a negative feedbackmode.
 4. The method of claim 1 wherein the reference stage includes areference current source and a reference transistor having a gatecoupled to a voltage reference and a drain coupled to the referencecurrent source.
 5. The method of claim 1 wherein the transistor of eachof the input stages includes a first current source, a gate coupled to anode and a source coupled to a source of a reference transistor, andwherein each of the input stages further includes: a second currentsource coupled to the node, a capacitor having a first terminal coupledto the node and a second terminal, a switch coupled between the firstand second terminals of the capacitor, and a logic block configured tolatch on the switch and turn off the switch for a subsequent input stagewhen a voltage at the node exceeds the reference voltage produced by thereference stage.
 6. The method of claim 1 wherein the two or more inputstages include just first and last stages, whereby the oscillator signalis a two phase oscillator signal.
 7. The method of claim 1 wherein thetwo or more input stages include just the first and last stages and anintermediate stage subsequent to the first stage and previous to thelast stage, whereby the oscillator signal is a three phase oscillatorsignal.
 8. The method of claim 1 wherein the two or more stages includejust the first and last stages, a first intermediate stage subsequent tothe first stage, and a second intermediate stage subsequent to the firstintermediate stage and previous to the last stage, whereby theoscillator signal is a four phase oscillator signal.